1. Field of the Invention
The present invention is generally related to high-performance peripheral data interfaces and, in particular, to a multi-threaded, bus-mastering, input/output (I/O) channel controller architecture applicable to general purpose personal computers, computer workstations, and embedded communications and network data routing and conversion functions.
2. Description of the Related Art
The continuing development of typically multimedia, network and communications oriented applications for personal computers and computer workstations is fundamentally dependant on performing computationally intensive operations on high data throughput digital data streams. Typically required computationally intensive operations include three dimensional (3D) audio generation and manipulation, wavetable based audio synthesis, V.34 protocol serial data signal generation and detection, and analog speech filtering and compression These operations, if implemented in software, will conventionally consume between 20 and 40 million instruction cycles per second each (MIPS) when performed by the main or host processor of the personal computer or workstation system. In addition, supporting the associated high throughput data stream transfer to conventional peripheral coder/decoder chips (CODECs) will consume an additional one to two MIPS per digital data transfer stream.
However, conventional microprocessors found in personal computer and workstation systems are generally capable of upwards of only 60 MIPS sustained, and more typically 20 to 30 MIPS. Context switches, memory management, and peripheral wait states further operate to constrain the effective MIPS available to computationally process and transport digital data streams. Since, as a practical matter, significant host processor MIPS must be reserved for the execution of typically end-user applications concurrent with the performance of multimedia functions, the need for peripheral hardware support in processing digital data streams has been generally acknowledged.
In adding peripheral hardware support for multimedia, network and communications applications, both hardware and software interface considerations need to be addressed. Any peripheral hardware used needs to be cost effective in adding computational functions without, in turn, burdening the host processor with hardware service requirements. Any added support burden directly compromises the net effective MIPS gain obtained through the addition of the peripheral hardware.
Similarly, the software interface to the peripheral hardware needs to efficiently interface with the operating system executed by the host processor to enable effective sustained use of the peripheral hardware. An ineffective software interface results in an increased MIPS commitment by the host processor to communicate with the peripheral hardware. Again, any increased processing burden due to complexities in managing the software interface to the peripheral hardware results in a direct reduction in the effective sustained processing MIPS obtained by use of the peripheral hardware.
Conventional approaches to providing peripheral hardware support for multimedia, network and communications applications include providing various combinations of dedicated integrated circuits (chips) implementing substantially hardwired or only partially configuration programmable computational functions and highly software programmable digital signal processors (DSPs). Dedicated function chips typically implement a limited signal processing function or small set of related functions in a low cost tightly packaged form. The supported functions are typically of specific functional scope and programmability is mostly restricted to initial configuration options and modest, if any, dynamic controls.
As a hardware peripheral, dedicated function chips typically provide little or no direct support for managing continuous real-time signal processing of digital data streams, let alone support for multiple data stream transport. Such chips typically act as mere consumers or producers (sources or sinks) of a digital data stream that is pulled from or pushed to the chips at the available maximum or some desired rate determined by the host processor. Consequently, peripheral hardware utilizing dedicated function chips is subject to conventional data stream transfer interruptions and transport speed limitations due to, for example, excessive host processor interrupts, context switching, and various memory management kernel processing, as well as a fundamental competition for host processor CPU cycles with other applications being concurrently executed by the host processor. System wide competition or limited system hardware support for multiple logically concurrent direct memory access (DMA) data transfers will also reduce sustained data transfer rates to a dedicated function chip. Furthermore, the typically single stream nature of dedicated function chips directly requires a substantial involvement by the host processor in performing data stream initialization, transport control and any required data stream mixing or multiplexing operations. Consequently, while dedicated function chips can provide a significant increase in the multimedia and digital signal processing capabilities of a personal computer or workstation system, a substantial and generally unbounded processing burden remains with the host processor.
General purpose digital signal processors have been implemented in peripheral hardware systems particularly where complex and high speed signal processing computations are required. Conventional DSP chips are capable of providing upwards of 50 MIPS in a computational architecture well suited for data stream processing. In general, such DSP chips are relatively expensive and require relatively intensive software development programs to implement the software algorithms needed to perform their intended functions. However, DSP chip architectures are generally not optimized for controlling extended data transfer operations or memory management functions. Rather, the architectures are typically optimized to read, process, and write data with respect to internal dedicated memory and external locally connected memory or directly connected dedicated function peripheral chips. Consequently, the host processor must again be substantially involved in data transfers to the memory space of a DSP implemented as peripheral hardware. Unfortunately, this generally results in the DSP being subject to the same limitations on the obtainable and sustainable performance of the host processor as in the case of dedicated function chips.
In order to bound interruptions in the transfer of data to multimedia peripheral hardware, and thereby improve the sustainable data transfer rate obtainable from a host processors a conventional operating system executed by the host processor may be augmented with a small, preemptive real-time kernel, such as SPOX. This kernel can be implemented as a low-level device driver supporting the real-time interrupt and data transfer requirements of the multimedia peripheral hardware. While such a real-time kernel does tend to ensure execution of maximum sustained data transfers to and from the DSP memory space, the host processor incurs the same substantial overhead of managing the data stream transfers as well as the additional execution overhead of the real-time kernel itself.
Consequently, present multimedia, network and communications peripheral hardware subsystems implemented typically for personal computers and workstation systems do not well address the need to efficiently provide additional processing capability through the addition of the peripheral hardware.
Various host based signal processing architectures, such as native signal processing (NSP) and Direct-X, have been proposed and largely defined to address, among several objectives, the requirement that a well formed software interface be provided to the operating system for multimedia, network and related communications operations. A host based signal processing architecture relies on the specific use of the host processor itself to perform at least high level signal processing functions. Such architectures have at least two immediate benefits. The first benefit is that, by significantly processing data streams before transport ultimately to peripheral hardware, the data streams are mixed, multiplexed or computationally reduced to lighten the processing overhead involved in the data transport to the peripheral hardware. Thus, the effective processing performance of the personal computer or workstation system may be slightly to significantly improved.
The second benefit is that a potentially comprehensive application programming interface (API) is presented to the operating system, thereby tending to virtualize particular implementations of the physical and functional peripheral hardware. Multimedia, network and related communications applications can therefore effectively assume broader or simply different support for desired functions than actually provided by any particular implementation of peripheral hardware. Where direct support for a particular function is not directly provided by a particular instance of the peripheral hardware, the function is performed in software by the host processor, executing as the host based signal processor, down to a functional level that is supported by the particular instance of the peripheral hardware.
While host based signal processing can increase the efficiency of the personal computer or workstation system in performing multimedia, network and communications functions, many of the functions supported by host based signal processing are still quite computationally intensive. Thus, host based signal processing represents a most direct burden on the host processor. Furthermore, while host based signal processing does have the potential for significantly reducing the volume of data transported to or from the peripheral hardware, as a practical matter the computational burden on the host processor will not be substantially affected and, in any event, will remain quite significant.